1. Field of the Invention
The present invention relates to a memory circuit and in particular to a memory circuit having at least one non-volatile memory cell and usually a plurality of non-volatile memory cells. In addition, the present invention particularly relates to memory circuits having EEPROM memory cells (EEPROM=electrically erasable and programmable read only memories) and to the set-up of a modified redundant EEPROM memory cell. Additionally, the invention relates to how the logic state (HIGH or LOW) of a memory cell can be read out so that it can be fed to another signal processing.
2. Description of Prior Art
EEPROM memory cells for very large-scale integration applications, as are, for example, to be found in portable computers, are, for example, known from xe2x80x9cAn enhanced 16K EEPROMxe2x80x9d, Lubin Gee, Pearl Cheng, Yogendra Bobra and Rustam Mehta, IEEE J. Sol. Stat. Circ., volume SC-17, no. 5, October 1982, pages 828 to 832 and from xe2x80x9cAn Experimental 4-Mb Flash EEPROM with Sector Erasexe2x80x9d, Mike McConnell and others, IEEE J. Sol. Stat. Circ., volume 26, no.4, April 1991, pages 484-491.
The set-up of memory cells is shown in FIGS. 1a and 1b. The memory cell shown in FIG. 1a includes an nMOS transistor 10 comprising a floating gate FG and a control gate CG. The control gate CG is connected to an input 12 of the memory cell. The drain of the nMOS transistor 10 is connected to an output 14 of the memory cell and to the drain of a pMOS transistor 16 serving for impressing a small reading voltage to the drain of the nMOS transistor 10. The source of the nMOS transistor 10 is connected to a reference potential of, for example, 0 V, i.e. ground. The source of the pMOS transistor 16 is connected to a supply voltage Vsup so that a supply voltage of the EEPROM memory cell shown in FIG. 1a is applied between the source of the pMOS transistor 16 and the source of the nMOS transistor 10.
The nMOS-EEPROM cell illustrated in FIG. 1a is such a cell as is typically used in VLSI technology (VLSI=very large-scale integration). Thus, above the channel of the nMOS transistor, there is a gate stack of a gate dielectric, a floating gate FG which is insulated from all the other parts of the circuit, another dielectric and the control gate CG. The gate dielectric directly above the channel is mostly formed as thin as possible while that between the floating gate FG and the control gate CG is thicker.
In FIG. 1b, an alternative EEPROM memory cell is shown in which a standard nMOS transistor 18 is used, the gate of which is connected to the input 12 of the memory cell via a capacitor 20. The gate electrode of the standard nMOS transistor 18 is thus insulated from all the other parts of the circuit by the capacitor 20 so that it represents a floating gate FG.
The fundamental functioning of a conventional EEPROM memory cell, as has been described above referring to FIGS. 1a and 1b, will be discussed subsequently. As has been explained, the gate of the nMOS transistor, directly above the channel, is insulated from all the other parts of the circuit, wherein the gate oxide, i.e. the dielectric between the floating gate FG and the channel, is, at least partly, formed thinner than usual. The floating gate is connected to a control gate via either a thicker dielectric (FIG. 1a) or via a capacitor (FIG. 1b), this set-up being electrically equivalent to an nMOS transistor, the gate FG of which is controlled via a capacity.
When the control gate CG is switched to a high voltage, usually between 10 V and 20 V, for a duration of about 10 ms, depending on the thickness of the gate oxide used, there is a voltage division according to the capacitive voltage divider by the capacities between CG and FG as well as between FG and the channel of the nMOS transistor. Since the gate oxide is thinner than the oxide between CG and FG, the capacity between FG and the channel of the nMOS transistor is larger than the capacity between CG and FG so that the bulk of the voltage difference applied between CG and the channel drops at the section CG-FG. The entire voltage must be large enough in order for the field strength in the gate oxide to be sufficient to let charge carriers tunnel from the channel through the gate oxide to the floating gate FG. This process is called Fowler-Nordheim tunneling. Thus a very small current flows. When the high voltage is finally switched off, the charge carriers are trapped at the floating gate FG since it is electrically insulated from its surroundings.
The charge carriers are thus at the floating gate and produce a voltage xcex94U at the coupling-in capacitor CG-FG so that the nMOS transistor is controlled by a gate voltage U(CG)-xcex94U, U(CG) being the voltage applied across the input 12 to the control gate of the memory cell.
When U(CG) is, for example, selected while reading out the memory cell such that an unprogrammed cell with xcex94U=0 V is just operated at the limit between conducting and blocking, the sign of xcex94U decides whether the nMOS transistor blocks or conducts. Depending on the definition used, xcex94U greater than 0 V is, for example, true for a programmed cell, while xcex94U less than 0 V is true for an erased cell. In order to read out the respective state from the memory cell, a small reading current is impressed via the pMOS transistor 16 into the drain of the nMOS transistor 10 and 18, respectively. A programmed nMOS transistor blocks so that its drain takes the logic state HIGH corresponding to the voltage Vsup. An erased nMOS transistor conducts so that its drain is pulled to LOW, about 0 V.
For reading out the cells of FIG. 1a or 1b, a reading current in the order of magnitude of 1 xcexcA is fed via the pMOS transistor 16 into the drain of the nMOS transistor 10 and 18, respectively, while a threshold voltage of the nMOS transistor is applied to the control gate CG. If the nMOS transistor is conductive, it will pull the output 14 to LOW. If the nMOS transistor blocks, the output will be HIGH. This reading process consumes power when the nMOS transistor 10 and 18, respectively, is conductive.
The capacitor 20 of the memory cell illustrated in FIG. 1b can, for example, be formed by a small poly-poly capacity with a capacitance of about 20 fF.
The reliability of well-known EEPROM memories, as are, for example, described above, can be increased by special coding methods. A simple possibility, for example, is to double-store each bit using two cells and to check in normal operation whether the two variations stored match. When they differ, an error must have occurred. For this method, the control gates of the two bits can be controlled by a common control circuit, which saves area, the two bits must, however, be read out separately and compared to each other, whereby the area consumption for the reading out circuit doubles.
In reality, it often occurs that a programmed xe2x80x9c1xe2x80x9d can become a xe2x80x9c0xe2x80x9d but the probability of a xe2x80x9c0xe2x80x9d becoming a xe2x80x9c1xe2x80x9d may be significantly lower. Thus, it is better to store a bit as a xe2x80x9c1xe2x80x9d and a xe2x80x9c0xe2x80x9d. The bit is recognized as being correct when the two pertaining memory cells are precisely programmed opposite to each other. Such an arrangement, however, requires even more chip area since, in this case, even the control circuit for the control gates of the two memory cells has to be formed separately. Thus also the area demand for storing a bit doubles compared to a simple storage with one cell per bit. Thus the increased reliability is only achieved by a serious chip area consumption.
In case a memory cell loses charge, it is at first not possible to reconstruct the original memory contents. In order to achieve this complicated methods have to be applied, as are developed in the theory for xe2x80x9cforward error codingxe2x80x9d. In this case, however, in addition to the information to be stored, redundant information from which an error case can be recognized and partly also corrected independently is stored as well. Thus these methods also require additional chip area since they need additional memory cells plus a control circuit for them.
Alternative non-volatile memory cells in which a common floating gate for a pMOS transistor and an nMOS transistor, which can be set up using a conventional CMOS technology, is used, are described in EP 0756328 A2 and in U.S. Pat. No. 6,028,789. In these non-volatile memory cells having a common floating gate, during reading operations, at least one of the two transistors will always block so that the power consumption is reduced.
The inventive memory circuit having a non-volatile memory cell, in contrast to the most often discussed very large scale integration variations, is to aim at those applications in which only about 100 bits are to be stored on an application-specific integrated circuit (ASIC). An exemplary application of this kind can, for example, apply to the adjustment or calibration of intelligent sensors in the module or in the element in which they are used. For such applications there are a number of specific features which are listed in the following enumeration:
1. A relatively small number of bits per ASIC is required, i.e. in the order of magnitude of 100.
2. The EEPROM memory cell is to be set up with possibly no changes in the process flow, i.e. without additional processing steps and masks, only with the standard elements available.
3. If a memory cell looses charge due to a defect, this may not lead to an incorrect memory contents, i.e. simple defects must be corrected automatically.
4. In the case of an emerging charge loss, the circuit should recognize this reliably and as early as possible in order to be able to react to this for example by notifying the user of the necessity of an urgent service.
5. The area demand of a memory cell is determined by the actual memory element only to a minor degree. The area demand of the control circuit which has to switch the high programming and erasing voltages to the respective cell is predominant.
6. When switching on the supply voltage to the ASIC, the entire memory contents must be readable at once. The matrix structure used in very large-scale integration EEPROMs is especially unsuitable for this for, in this case, the memory has to be read out per line, column or page.
7. In normal operation the memory should consume as little static power as possible.
8. The memory cell should be as reliable as possible, especially when the ASIC is employed in automobile technology or other high-security applications. What follows is, for example, that only a static, but no dynamic, logic is allowed to be used. As another consequence this leads to the concept that an EEPROM cell is, for example, read out by a continuous reading signal. This is in contrast to dynamic methods in which a pulsed reading signal is used. In the continuous case, the EEPROM cell does not need to be as fast as possible so that the inventive usage of slower pMOS transistors can be justified.
9. The circuit-technological overhead must be kept as low as possible, in particular in ASICs having a small chip area.
It is the object of the present invention to provide a memory circuit having a non-volatile memory cell allowing setting up a high-reliability memory.
This object is achieved by a memory circuit having a non-volatile memory cell, the non-volatile memory cell comprising:
an enhancement pMOS transistor having a floating gate;
an enhancement nMOS transistor having a floating gate insulated from the floating gate of the pMOS transistor;
a control input capacitively coupled to the floating gate of the pMOS transistor and to the floating gate of the nMOS transistor,
the pMOS transistor and the nMOS transistor being connected by a connection point and the connection point being connected to an output of the memory cell,
the pMOS transistor additionally being connected to a first terminal of the memory cell and the nMOS transistor being further connected to a second terminal of the memory cell, wherein a supply voltage can be applied to the memory cell via the first and second terminals.
The pMOS transistor and the nMOS transistor are preferably formed in CMOS technology, the drains of the pMOS transistor and of the nMOS transistor being connected to each other and to an output of the memory cell, the source of the pMOS transistor being connected to the first terminal and the source of the nMOS transistor being connected to the second terminal. In general, in the non-volatile memory cell of the inventive memory circuit, one source/drain region of each of the pMOS transistor and the nMOS transistor are connected to each other in order to implement a series connection of the two transistors, the connecting point being connected to the output of the memory cell, while the respective non-connected source/drain region of the nMOS transistor and the pMOS transistor is connected to a respective supply voltage terminal.
The inventive non-volatile memory cell thus, apart from a conventional nMOS memory cell, comprises an additional pMOS memory cell having, like the nMOS memory cell, its own floating gate. When, due to a local defect, the charge at the floating gate of the nMOS memory cell is lost, the charge at the floating gate of the pMOS memory cell remains. Thus the inventive non-volatile memory cell can be referred to as redundant since a bit in the form of charges is stored at two different nodes of the network. Since the pMOS transistor and the nMOS transistor are connected to each other similarly to what is the case in a CMOS inverter, the inventive non-volatile memory cell can be referred to as a CMOS-EEPROM.
The inventive memory circuit can further comprise control means for applying suitable writing voltages, erasing voltages and reading voltages to the input of the memory cell. In addition, means can be provided in preferred embodiments in order to detect a cross current between the first and second terminals of the non-volatile memory chip or to judge the charge state of the floating gates of the transistors.
Developments of the inventive memory circuit include advantageous embodiments for an MOS transistor arrangement for applying and removing charges to the floating gates of the non-volatile memory cell. In addition, developments of the inventive memory cell include a current watch circuit for monitoring a current between the first and second terminals when the supply voltage is applied between them, while at the same time the readiness for operation of the memory cell is maintained.
In a development of the inventive memory cell, it is coupled to a CMOS inverter in such a way that the output of the memory cell is connected to the input of the CMOS inverter, while the input of the memory cell is connected to the output of the CMOS inverter. In such a connection the memory cell can be read out without applying a reading voltage to the control input.
Further redundancy can be added to the inventive memory circuit by providing the non-volatile memory cell with a second enhancement pMOS transistor having a floating gate and being connected in parallel to the other enhancement pMOS transistor having a floating gate and by providing the non-volatile memory cell with a second enhancement nMOS transistor having a floating gate and being connected in parallel to the other self-blockage nMOS transistor.
Such and further developments of the present invention are stated in the dependent claims.